Conventional synchronous DRAM (SDRAM) devices may include multiple banks of memory cells and operations to write and read data to and from these multiple memory banks may be synchronized to a clock signal. Conventional SDRAM devices may also include a plurality of row decoders so that word lines within each bank of memory cells can be controlled in an interleaved fashion to improve data transfer efficiency. This is unlike other conventional and less efficient DRAM devices which require the deactivation of a word line before activation of another word line. Accordingly, SDRAM devices can typically access and transfer a greater quantity of data at a faster rate than conventional DRAM devices. A conventional multi-bank SDRAM device is also described in a textbook by Steven A. Przybylski, entitled "New Dram Technologies", MicroDesign Resources, ISBN 1-885330-06-5, pp. 219-222 (1996).
Referring now to FIG. 1, a timing diagram which illustrates operation of a multi-bank SDRAM device according to the prior art is provided. In particular, the timing diagram illustrates an interleaved read operation during burst mode operation (with the length of the burst programmed to be 4). The RAS and CAS latencies, which are intervals between the activation of the row and column address strobe signals /RAS and /CAS and the data output DQ, are programmed to be 4 and 1, respectively. Here, the /RAS signal and a row address Ax for bank A are provided to select one of the word lines in bank A, and then a /CAS signal and a column address Ax for bank A are input after a predetermined time period. The data in the selected memory cells in bank A (DA0-DA3) are then output in synchronization with the CLK. Next, the /RAS signal and a row address Ax for bank B are provided to select one of the word lines in bank B, and then a /CAS signal and a column address Ax for bank B are input after a predetermined time period. The data in the selected memory cells in bank B (DB0-DB3) are then output in synchronization with the CLK. Unfortunately, although the data access rate for such conventional SDRAM devices can be increased by providing a row address for bank B while the data DA0-DA3 in bank A is being accessed, such conventional SDRAM devices typically require one row decoder and one column decoder for each memory bank which increases layout area.
Thus, notwithstanding the above-described multi-bank memory devices, there continues to be a need for improved memory devices have efficient data access capability and reduced layout area requirements.